| Automotive | |||
| March 23, 2017 | |||
| 12:00 pm - 1:30 pm | Hall A1 | Automotive IP Lunch & Learn: Under The Hood: What It Takes To Meet Automotive Compliance [More Info] | |
| Backend Implementation | |||
| March 23, 2017 | |||
| 10:30 am - 11:15 am | Hall A2 | Accelerating Interconnect Timing Closure with Synopsys Design Compiler Graphical and IC Compiler II [More Info] Speaker: Monica Tang, Applications Engineering Manager, Arteris Speaker: Kurt Shuler, Arteris | |
| 11:15 am - 12:00 pm | Hall A2 | The Faster, Better, and Shorter ICC II – How It’s Done with ARM POPTM IP for Cortex®-A73 [More Info] Speaker: Rupal Gandhi, ARM | |
| 1:30 pm - 2:20 pm | Hall A2 | Pipeline Register Planning [More Info] Speaker: David Peart, Synopsys | |
| 2:20 pm - 3:10 pm | Hall A2 | GLOBALFOUNDRIES 7nm RTL to GDS Flow [More Info] Speaker: Haritez Narisetty, GLOBALFOUNDRIES | |
| 3:30 pm - 4:15 pm | Hall A2 | IC Validator Fill Methodologies on GF 7nm [More Info] Speaker: Rohit Bhelkar, MTS Design Enablement, GLOBALFOUNDRIES | |
| 4:15 pm - 5:00 pm | Hall A2 | Physical Verification In-Design Flow within IC Compiler and Signoff Flows [More Info] Speaker: Li-Siang Lee, Barefoot Networks | |
| Custom Design & AMS | |||
| March 23, 2017 | |||
| 10:30 am - 11:15 am | Room 203/204 | GLOBALFOUNDRIES 22FDX Custom Design Flow with Synopsys Custom Compiler [More Info] Speaker: Jignesh Patel, GLOBALFOUNDRIES | |
| 11:15 am - 12:00 pm | Room 203/204 | Using Custom Compiler and IC Compiler for Layout of Memory and APU Networking SoC [More Info] Speaker: Randy You, GSI Technology | |
| 12:00 pm - 1:30 pm | Mission City Ballroom | Custom Compiler Lunch & Learn: Cutting FinFET Layout Tasks from Days to Hours [More Info] | |
| 1:30 pm - 2:20 pm | Room 203/204 | Using Custom Compiler’s Visually-Assisted Automation for Analog Layout [More Info] Speaker: Jimmy Lin, Synopsys | |
| 2:20 pm - 3:10 pm | Room 203/204 | Rapid Layout of 7nm Custom Digital Designs Using Custom Compiler [More Info] Speaker: Harry Yuan, Synopsys | |
| 3:30 pm - 4:15 pm | Room 203/204 | Self-Heat Aware Electro-Migration (EM) Simulation and Analysis with CustomSim for FinFET Devices and Smaller Geometries [More Info] Speaker: Haran Thanikasalam, Synopsys | |
| Frontend Implementation | |||
| March 23, 2017 | |||
| 10:30 am - 11:15 am | Hall A3 | Hierarchical Design Exploration to Find Automatic Body Bias Configuration to Achieve Optimal PPA for GLOBALFOUNDRIES 22 FD-SOI Technology [More Info] Speaker: Pratik Rajput, MTS Design Engineer, GLOBALFOUNDRIES | |
| 11:15 am - 12:00 pm | Hall A3 | Network On a Chip (NoC) Fabric Timing Closure for an Advanced Low Power SoC [More Info] Speaker: Joon Yoon, Director, Silicon Design, Microsoft Speaker: Sarvesh Ganesan, Silicon Design Engineer, Microsoft | |
| 12:00 pm - 1:30 pm | Hall B | Design Compiler Lunch & Learn: Advanced Silicon Design Success with Design Compiler [More Info] | |
| 1:30 pm - 2:20 pm | Hall A3 | Galaxy RTL: Design Compiler Family 2016.12 Update [More Info] Speaker: Bob Wiegand, Synopsys | |
| 2:20 pm - 3:10 pm | Hall A3 | Accelerating ECO Implementation Using Formality Ultra [More Info] | |
| 3:30 pm - 5:00 pm | Hall A3 | Principles of Low Power Design Using UPF [More Info] Speaker: Matt Dittrich, Synopsys | |
| General Sessions | |||
| March 23, 2017 | |||
| 9:00 am - 10:00 am | Mission City Ballroom | Keynote - Learning and Multiagent Reasoning for Autonomous Robots [More Info] Speaker: Dr. Peter Stone, David Bruton, Jr. Centennial Professor of Computer Science, The University of Texas at Austin and Cogitai, Inc. | |
| IP Summit | |||
| March 23, 2017 | |||
| 10:30 am - 11:15 am | Ballroom G | DDR4 or HBM2 High Bandwidth Memory: How To Choose Now [More Info] Speaker: Graham Allan, Synopsys | |
| 11:15 am - 12:00 pm | Ballroom G | Designing in PCI Express 4.0 and CCIX for Cache Coherency [More Info] Speaker: Richard Solomon, Synopsys | |
| 12:00 pm - 1:30 pm | Hall A1 | Automotive IP Lunch & Learn: Under The Hood: What It Takes To Meet Automotive Compliance [More Info] | |
| 1:30 pm - 2:20 pm | Ballroom G | Building Security In Your SoC With A Hardware Root of Trust Secure Module [More Info] Speaker: Andrew Elias, Synopsys | |
| 2:20 pm - 3:10 pm | Ballroom G | Integrating USB3.0 Controller and Intel USB2.0 and HSIC PHY's [More Info] | |
| 3:30 pm - 4:15 pm | Ballroom G | USB Type-C Connects Them All [More Info] Speaker: Morten Christiansen, Synopsys | |
| Lunch & Learn | |||
| March 23, 2017 | |||
| 12:00 pm - 1:30 pm | Hall A1 | Automotive IP Lunch & Learn: Under The Hood: What It Takes To Meet Automotive Compliance [More Info] | |
| 12:00 pm - 1:30 pm | Mission City Ballroom | Custom Compiler Lunch & Learn: Cutting FinFET Layout Tasks from Days to Hours [More Info] | |
| 12:00 pm - 1:30 pm | Hall B | Design Compiler Lunch & Learn: Advanced Silicon Design Success with Design Compiler [More Info] | |
| Networking Opportunities | |||
| March 23, 2017 | |||
| 8:00 am - 8:45 am | Lobby | Breakfast [More Info] | |
| 8:00 am - 6:00 pm | Lobby | Registration [More Info] | |
| 12:00 pm - 1:30 pm | Hall D | Networking Lunch [More Info] | |
| 5:00 pm - 6:30 pm | Mission City Ballroom | Awards and SNUG After Party* [More Info] | |
| Signoff & Characterization | |||
| March 23, 2017 | |||
| 10:30 am - 11:15 am | Great America J | On the Mathematical Principles of Interface Timing Constraints [More Info] | |
| 10:30 am - 11:15 am | Great America K | Setup, Use and Validation of POCV in NanoTime from a User's Perspective [More Info] Speaker: Robert Murray, Sr. Asic Design Engineer, NVIDIA | |
| 11:15 am - 12:00 pm | Great America J | Static Timing Fundamentals [More Info] Speaker: Jason Rziha, Sr. EDA CAD Engineer, Microchip Technology | |
| 11:15 am - 12:00 pm | Great America K | Timing Analysis and Signoff for Ultra High Speed Processor Design Using NanoTime [More Info] Speaker: Roger Carpenter, VP, Design Methodology, Wave Computing | |
| 1:30 pm - 2:20 pm | Great America K | Cell Level Electromigration Characterization in SiliconSmart [More Info] Speaker: Jing Li, Senior Engineer, Qualcomm Technologies | |
| 1:30 pm - 3:10 pm | Great America J | PrimeTime ECO – Introducing Clock ECO [More Info] Speaker: Troy Epperly, Synopsys | |
| 2:20 pm - 3:10 pm | Great America K | ESP for Library Verification [More Info] Speaker: Dave Hedges, Synopsys | |
| 3:30 pm - 4:15 pm | Great America J | Merging Modal STA Constraints to Reduce Timing Closure Complexity [More Info] Speaker: Michael Batek, Senior Technical Director, Broadcom | |
| 4:15 pm - 5:00 pm | Great America J | Higher Productivity and Faster TAT Through Flow Automation [More Info] Speaker: Suresh Raman, CAD Director , Xilinx | |
| Test | |||
| March 23, 2017 | |||
| 10:30 am - 11:15 am | Ballroom H | Cell-Aware Test for Lower DPPM and Faster Silicon Diagnosis [More Info] Speaker: Brian Archer, Synopsys Speaker: Chris Schuermyer, Synopsys | |
| 11:15 am - 12:00 pm | Ballroom H | Accelerating Silicon Diagnosis Using a Cell-Aware Flow [More Info] Speaker: Nelly Feldman, Diagnosis Engineer, STMicroelectronics | |
| 1:30 pm - 2:20 pm | Ballroom H | Advanced Memory Test and Repair with SMS and Hierarchical Test and Diagnosis from IPs to SoC with SHS [More Info] Speaker: Yervant Zorian, Synopsys | |
| User Content Reviewed by the Technical Committee | |||
| March 23, 2017 | |||
| 10:30 am - 11:15 am | Mission City 1 | A Journey to a Successful VIP Migration: A PCI-Express Testbench Case Study [More Info] Speaker: Chien-Chih Yu, Senior Engineer, Oracle | |
| 10:30 am - 11:15 am | Hall A2 | Accelerating Interconnect Timing Closure with Synopsys Design Compiler Graphical and IC Compiler II [More Info] Speaker: Monica Tang, Applications Engineering Manager, Arteris Speaker: Kurt Shuler, Arteris | |
| 10:30 am - 11:15 am | Mission City 2 | Finding Inefficient Clock Gating With Gate Level Simulations and PrimeTime PX Based Clock Activity Binning [More Info] Speaker: Samuel Intiso, Experienced Engineer, Axis Communications | |
| 10:30 am - 11:15 am | Hall A3 | Hierarchical Design Exploration to Find Automatic Body Bias Configuration to Achieve Optimal PPA for GLOBALFOUNDRIES 22 FD-SOI Technology [More Info] Speaker: Pratik Rajput, MTS Design Engineer, GLOBALFOUNDRIES | |
| 10:30 am - 11:15 am | Great America J | On the Mathematical Principles of Interface Timing Constraints [More Info] | |
| 10:30 am - 11:15 am | Great America K | Setup, Use and Validation of POCV in NanoTime from a User's Perspective [More Info] Speaker: Robert Murray, Sr. Asic Design Engineer, NVIDIA | |
| 11:15 am - 12:00 pm | Hall A3 | Network On a Chip (NoC) Fabric Timing Closure for an Advanced Low Power SoC [More Info] Speaker: Joon Yoon, Director, Silicon Design, Microsoft Speaker: Sarvesh Ganesan, Silicon Design Engineer, Microsoft | |
| 11:15 am - 12:00 pm | Mission City 2 | Optimal Power Design and Verification For An Advanced Low Power ASIC [More Info] Speaker: Tim Balbekov, Silicon Design Engineer, Microsoft Speaker: Anand Iyer, Senior Design Engineer, Microsoft | |
| 11:15 am - 12:00 pm | Great America J | Static Timing Fundamentals [More Info] Speaker: Jason Rziha, Sr. EDA CAD Engineer, Microchip Technology | |
| 11:15 am - 12:00 pm | Great America K | Timing Analysis and Signoff for Ultra High Speed Processor Design Using NanoTime [More Info] Speaker: Roger Carpenter, VP, Design Methodology, Wave Computing | |
| 1:30 pm - 2:20 pm | Great America K | Cell Level Electromigration Characterization in SiliconSmart [More Info] Speaker: Jing Li, Senior Engineer, Qualcomm Technologies | |
| 1:30 pm - 2:20 pm | Mission City 1 | Formally Improving Coverage in SoC Verification [More Info] | |
| 1:30 pm - 2:20 pm | Room 209 | Modular Virtual x86 CPU Subsystem for Fast Creation of SoC Virtual Platforms [More Info] | |
| 2:20 pm - 3:10 pm | Ballroom G | Integrating USB3.0 Controller and Intel USB2.0 and HSIC PHY's [More Info] | |
| 2:20 pm - 3:10 pm | Mission City 1 | Reaching the Elusive Goal of 100% Coverage Target [More Info] Speaker: Munjal Chudgar, Technical Lead, Cisco Systems | |
| 3:30 pm - 4:15 pm | Great America J | Merging Modal STA Constraints to Reduce Timing Closure Complexity [More Info] Speaker: Michael Batek, Senior Technical Director, Broadcom | |
| Verification Continuum III (FPGA & Prototyping) | |||
| March 23, 2017 | |||
| 10:30 am - 11:15 am | Room 209 | Fault Injection Testing of SSD Controller Software Using the Virtualizer SSD Reference VDK [More Info] Speaker: Filip Thoen, Synopsys | |
| 11:15 am - 12:00 pm | Room 209 | Building and Deploying the Tegra System Virtual Prototype [More Info] Speaker: Ling Yang, NVIDIA | |
| 1:30 pm - 2:20 pm | Room 209 | Modular Virtual x86 CPU Subsystem for Fast Creation of SoC Virtual Platforms [More Info] | |
| 2:20 pm - 3:10 pm | Room 209 | Enabling Functional Safety for FPGA Based Hardware Design [More Info] | |
| 3:30 pm - 5:00 pm | Room 209 | Optimizing Heterogeneous Multicore Cache Coherent Subsystem Architecture Using Synopsys Platform Architect and Arteris Ncore IP [More Info] Speaker: Matthew Mangan, Arteris Speaker: Pat Sheridan, Synopsys | |
| Verification Continuum | |||
| March 23, 2017 | |||
| 10:30 am - 11:15 am | Mission City 1 | A Journey to a Successful VIP Migration: A PCI-Express Testbench Case Study [More Info] Speaker: Chien-Chih Yu, Senior Engineer, Oracle | |
| 10:30 am - 11:15 am | Mission City 2 | Finding Inefficient Clock Gating With Gate Level Simulations and PrimeTime PX Based Clock Activity Binning [More Info] Speaker: Samuel Intiso, Experienced Engineer, Axis Communications | |
| 11:15 am - 12:00 pm | Mission City 1 | Addressing the Challenges in Verifying Next-Generation Network Products [More Info] Speaker: Jaspreet Singh Gambhir, Synopsys | |
| 11:15 am - 12:00 pm | Mission City 2 | Optimal Power Design and Verification For An Advanced Low Power ASIC [More Info] Speaker: Tim Balbekov, Silicon Design Engineer, Microsoft Speaker: Anand Iyer, Senior Design Engineer, Microsoft | |
| 1:30 pm - 2:20 pm | Mission City 2 | A “Completely Cool” Case Study – Synopsys Low Power Frontend Verification [More Info] Speaker: Karan Brar, Synopsys | |
| 1:30 pm - 2:20 pm | Mission City 1 | Formally Improving Coverage in SoC Verification [More Info] | |
| 2:20 pm - 3:10 pm | Mission City 2 | A “Completely Cool” Case Study – Synopsys Low Power Frontend Implementation [More Info] Speaker: Antonio Dimalanta, Synopsys | |
| 2:20 pm - 3:10 pm | Mission City 1 | Reaching the Elusive Goal of 100% Coverage Target [More Info] Speaker: Munjal Chudgar, Technical Lead, Cisco Systems | |
| 3:30 pm - 4:15 pm | Mission City 1 | Boosting Debug Productivity – Practical Applications of Verdi Debug Innovations [More Info] Speaker: Alex Wakefield, Synopsys | |
| 3:30 pm - 4:15 pm | Ballroom H | Understanding Clock-Gating to Optimize Power at RTL [More Info] Speaker: Ken Mason, Synopsys | |
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