| Automotive | |||
| March 22, 2017 | |||
| 11:00 am - 11:45 am | Ballroom G | An Efficient and Accelerated Approach to Fault Injection and Diagnostic Coverage Calculations of a Complex SoC [More Info] | |
| 11:45 am - 12:30 pm | Ballroom G | ISO26262 Functional Safety Metrics: Journey from Concept to Certification [More Info] Speaker: Meirav Nitzan, Verification Methodologist, Xilinx | |
| 2:00 pm - 2:45 pm | Ballroom G | Panel: Safety Critical Automotive Designs, What's The Difference? [More Info] Speaker: Richard Bramley, Functional Safety Architect, NVIDIA Speaker: John Hayden, Systems Architect for Functional Safety, Analog Devices Inc Speaker: Srini Krishnaswami, Synopsys | |
| 2:45 pm - 3:30 pm | Ballroom G | Practical Fault Sampling and Coverage Estimation for Functional Safety of Large SoCs [More Info] Speaker: Amitava Majumdar, Principal Engineer, Xilinx | |
| 3:45 pm - 4:30 pm | Ballroom G | Synopsys Automotive Test - ISO 26262-Certified Solution [More Info] Speaker: Adam Cron, Synopsys Speaker: Yervant Zorian, Synopsys | |
| 4:30 pm - 5:15 pm | Ballroom G | Meeting IP Requirements of ADAS Automotive SoCs [More Info] Speaker: Ron DiGiuseppe, Synopsys | |
| Backend Implementation | |||
| March 22, 2017 | |||
| 11:00 am - 11:45 am | Mission City 1 | Emulated FILL in ICC II for Tighter Timing Signoff [More Info] Speaker: Babitha Bommalakunta, MTS Design Enablement, GLOBALFOUNDRIES | |
| 11:45 am - 12:30 pm | Mission City 1 | Implementation of Hybrid Clock Tree Synthesis [More Info] Speaker: Yi Zhang, Senior Physical Design Engineer, NVIDIA | |
| 12:30 pm - 2:00 pm | Mission City Ballroom | IC Compiler II Lunch & Learn: Achieving Industry-Best QoR on Advanced Designs [More Info] | |
| 2:00 pm - 2:45 pm | Mission City 1 | ICCII 2016.12 Update [More Info] Speaker: Thomas McLaughlin, Synopsys | |
| 2:45 pm - 3:30 pm | Mission City 1 | Enabling Rapid Integration of Complex IPs for SoC Designs [More Info] | |
| 3:45 pm - 5:15 pm | Mission City 1 | Best Practices for High-Performance, Energy Efficient Implementations of the Latest ARM® Processors in 16-nanometer FinFET Compact (16FFC) Process Technology Using Synopsys Galaxy™ Design Platform [More Info] Speaker: Vidit Babbar, ARM Speaker: Joe Walston, Synopsys | |
| Custom Design & AMS | |||
| March 22, 2017 | |||
| 11:00 am - 11:45 am | Room 203/204 | Stacked Device Enablement for FinFET Simulation in HSPICE [More Info] Speaker: Jane Xi, Senior Staff R&D, Xilinx | |
| 11:45 am - 12:30 pm | Room 203/204 | M-2017.03 HSPICE®, FineSim SPICE® and Custom WaveView® Update Training [More Info] Speaker: Szekit Chan, Synopsys | |
| 2:00 pm - 2:45 pm | Room 203/204 | Variability Analysis in CustomSim Using Monte Carlo [More Info] Speaker: Raed Sabbah, Staff Engineer , Micron Technology | |
| 2:45 pm - 3:30 pm | Room 203/204 | Handling of VCO Switching of LC-PLL Verification with Advanced Features in VCS AMS (CustomSim-VCS) [More Info] Speaker: Tony Cai, Engineer, Xilinx | |
| 3:45 pm - 4:30 pm | Room 203/204 | Addressing Circuit Simulation Challenges in Advanced Node Designs Using CustomSim [More Info] Speaker: James Han, Synopsys | |
| 4:30 pm - 5:15 pm | Room 203/204 | Efficient Monte Carlo Solution - Custom Compiler™ Simulation Analysis Environment Using HSPICE®, FineSim™, and CustomSim™ [More Info] Speaker: Preeti Jain, Synopsys | |
| Frontend Implementation | |||
| March 22, 2017 | |||
| 11:00 am - 12:30 pm | Theater | Panel: RTL Synthesis Vision Into The Next Decade [More Info] | |
| 2:00 pm - 2:45 pm | Mission City 2 | RTL FSM Coding for Predictive Synthesis [More Info] | |
| 2:45 pm - 3:30 pm | Mission City 2 | Synthesizable SystemVerilog for Scalable and Reusable Designs: The Journey until 2012 and a Wish List for Beyond [More Info] Speaker: Abhirami Senthilkumaran, Senior Engineer, Qualcomm Technologies | |
| 3:45 pm - 4:30 pm | Mission City 2 | Selective Ungroup Synthesis Approach in High Speed DSP Design [More Info] Speaker: Hailan Zhu, Principal Design Engineer, Broadcom | |
| 4:30 pm - 5:15 pm | Mission City 2 | Design for Reconfigurability [More Info] Speaker: Kalyana S Venkataraman, Hardware Design Engineer , Cavium | |
| General Sessions | |||
| March 22, 2017 | |||
| 9:00 am - 10:30 am | Mission City Ballroom | Silicon to Software to Smart Everything [More Info] Speaker: Dr. Aart de Geus, Chairman & co-CEO, Synopsys | |
| Lunch & Learn | |||
| March 22, 2017 | |||
| 12:30 pm - 2:00 pm | Mission City Ballroom | IC Compiler II Lunch & Learn: Achieving Industry-Best QoR on Advanced Designs [More Info] | |
| 12:30 pm - 2:00 pm | Hall A1 | Verification Lunch & Learn: SoC Leaders Verify with Synopsys [More Info] | |
| Networking Opportunities | |||
| March 22, 2017 | |||
| 7:30 am - 8:45 am | Lobby | Breakfast [More Info] | |
| 7:30 am - 6:00 pm | Lobby | Registration [More Info] | |
| 12:30 pm - 2:00 pm | Hall D | Networking Lunch [More Info] | |
| 5:15 pm - 7:00 pm | Hall B | SNUG Pub [More Info] | |
| Signoff & Characterization | |||
| March 22, 2017 | |||
| 11:00 am - 11:45 am | Great America K | Clock Domain Bridge Static Timing Analysis [More Info] Speaker: Miles Simpson, Design Engineer, Microsoft | |
| 11:00 am - 12:30 pm | Great America J | The Next Generation of HyperScale – Speed, Resource Efficiency and Added Flexibility [More Info] Speaker: Jem Lin, Synopsys | |
| 11:45 am - 12:30 pm | Great America K | Using Cerberus Technology to Bring a Data-Driven Approach to Chip Design [More Info] Speaker: Sashi Obilisetty, Synopsys | |
| 2:00 pm - 2:45 pm | Great America J | Advanced Techniques to Reduce the Crosstalk Pessimism in the PrimeTimeSI Timing Analysis [More Info] Speaker: Stella Matarrese, Senior Principal Engineer, STMicroelectronics | |
| 2:00 pm - 2:30 pm | Great America K | Parasitic Extraction Advances for 7nm PDK Enablement [More Info] Speaker: Srilata Raman, Parasitic Extraction Engineer, GLOBALFOUNDRIES | |
| 2:30 pm - 3:00 pm | Great America K | StarRC Update – 7nm Accuracy, Performance, and Interactive Custom Design Efficiency [More Info] Speaker: Krishnakumar Sundaresan, Synopsys Speaker: Denis Goinard, Synopsys | |
| 2:45 pm - 3:30 pm | Great America J | Using PrimeTime POCV To Maximize Design Robustness For Ultra-low Voltage FinFET Designs [More Info] Speaker: Duc Huynh, Synopsys | |
| 3:00 pm - 3:30 pm | Great America K | Juniper’s Experience Using StarRC to Speed Turnaround Time for 16nm Networking Chips [More Info] Speaker: Narayan Subramanian, Juniper | |
| 3:45 pm - 5:15 pm | Great America J/K | Panel: Automotive Chip Signoff - Autonomous or Requires Driver Assistance? [More Info] | |
| Test | |||
| March 22, 2017 | |||
| 11:00 am - 11:45 am | Ballroom H | Meet Your Test Quality and Cost Goals with Unprecedented Speed [More Info] Speaker: Adam Cron, Synopsys | |
| 11:45 am - 12:30 pm | Ballroom H | TetraMAX II: ATPG Moves Into the 21st Century [More Info] Speaker: Jonathon Colburn, Distinguished Engineer, NVIDIA | |
| 2:00 pm - 2:45 pm | Ballroom H | SpyGlass® DFT ADV: High Testability, SoC Connectivity, Functional Safety and Reliability [More Info] Speaker: Fadi Maamari, Synopsys | |
| 2:45 pm - 3:30 pm | Ballroom H | Improving SoC Testability as Part of RTL Signoff [More Info] Speaker: Nathan Hsiung, Master Engineer, Broadcom | |
| 3:45 pm - 4:30 pm | Ballroom H | Reducing Scan Test Times by Post-ATPG Optimization of DFTMAX Ultra Patterns [More Info] Speaker: Richard Illman, Member of Technical Staff, Dialog Semiconductor | |
| 4:30 pm - 5:15 pm | Ballroom H | Stuck at Pattern Generation Using Internal Clocking Procedure [More Info] Speaker: Ashok Mathur, Senior Member Technical Staff, AMD | |
| User Content Reviewed by the Technical Committee | |||
| March 22, 2017 | |||
| 11:00 am - 11:45 am | Ballroom G | An Efficient and Accelerated Approach to Fault Injection and Diagnostic Coverage Calculations of a Complex SoC [More Info] | |
| 11:00 am - 11:45 am | Great America K | Clock Domain Bridge Static Timing Analysis [More Info] Speaker: Miles Simpson, Design Engineer, Microsoft | |
| 11:00 am - 11:45 am | Mission City 1 | Emulated FILL in ICC II for Tighter Timing Signoff [More Info] Speaker: Babitha Bommalakunta, MTS Design Enablement, GLOBALFOUNDRIES | |
| 11:00 am - 11:45 am | Room 203/204 | Stacked Device Enablement for FinFET Simulation in HSPICE [More Info] Speaker: Jane Xi, Senior Staff R&D, Xilinx | |
| 11:00 am - 11:45 am | Room 209 | Widening the Scope and Adoption of FPGA-based Physical Prototyping at ARM [More Info] Speaker: Peter Fogl, Senior Engineer, ARM Ltd | |
| 11:45 am - 12:30 pm | Mission City 1 | Implementation of Hybrid Clock Tree Synthesis [More Info] Speaker: Yi Zhang, Senior Physical Design Engineer, NVIDIA | |
| 11:45 am - 12:30 pm | Ballroom G | ISO26262 Functional Safety Metrics: Journey from Concept to Certification [More Info] Speaker: Meirav Nitzan, Verification Methodologist, Xilinx | |
| 11:45 am - 12:30 pm | Ballroom H | TetraMAX II: ATPG Moves Into the 21st Century [More Info] Speaker: Jonathon Colburn, Distinguished Engineer, NVIDIA | |
| 11:45 am - 12:30 pm | Room 209 | Trapping the Hardest to Find Hardware Bugs in the Latest ARM Cores Using FPGA-based HAPS Debug Technologies [More Info] Speaker: Peter Gibbons, Senior FPGA Engineer, ARM Ltd. | |
| 2:00 pm - 2:45 pm | Great America J | Advanced Techniques to Reduce the Crosstalk Pessimism in the PrimeTimeSI Timing Analysis [More Info] Speaker: Stella Matarrese, Senior Principal Engineer, STMicroelectronics | |
| 2:00 pm - 2:30 pm | Great America K | Parasitic Extraction Advances for 7nm PDK Enablement [More Info] Speaker: Srilata Raman, Parasitic Extraction Engineer, GLOBALFOUNDRIES | |
| 2:00 pm - 2:45 pm | Hall A3 | Reusable Compile Snapshot for Scaling Down Compilation Time Towards Modern SoC Verification [More Info] Speaker: Akshay Shukla, Sr. Engineer, eInfochips Inc | |
| 2:00 pm - 2:45 pm | Mission City 2 | RTL FSM Coding for Predictive Synthesis [More Info] | |
| 2:00 pm - 2:45 pm | Room 203/204 | Variability Analysis in CustomSim Using Monte Carlo [More Info] Speaker: Raed Sabbah, Staff Engineer , Micron Technology | |
| 2:45 pm - 3:30 pm | Hall A3 | A Simple RTL IP Obfuscation Flow - Using Synopsys VCS, DC and Formality [More Info] Speaker: David Flynn, Fellow, ARM Ltd | |
| 2:45 pm - 3:30 pm | Mission City 1 | Enabling Rapid Integration of Complex IPs for SoC Designs [More Info] | |
| 2:45 pm - 3:30 pm | Room 203/204 | Handling of VCO Switching of LC-PLL Verification with Advanced Features in VCS AMS (CustomSim-VCS) [More Info] Speaker: Tony Cai, Engineer, Xilinx | |
| 2:45 pm - 3:30 pm | Ballroom H | Improving SoC Testability as Part of RTL Signoff [More Info] Speaker: Nathan Hsiung, Master Engineer, Broadcom | |
| 2:45 pm - 3:30 pm | Ballroom G | Practical Fault Sampling and Coverage Estimation for Functional Safety of Large SoCs [More Info] Speaker: Amitava Majumdar, Principal Engineer, Xilinx | |
| 2:45 pm - 3:30 pm | Mission City 2 | Synthesizable SystemVerilog for Scalable and Reusable Designs: The Journey until 2012 and a Wish List for Beyond [More Info] Speaker: Abhirami Senthilkumaran, Senior Engineer, Qualcomm Technologies | |
| 3:45 pm - 4:30 pm | Room 209 | Effective Methodology for Latch-based Design – CPU Prototyping on HAPS Platform [More Info] | |
| 3:45 pm - 4:30 pm | Ballroom H | Reducing Scan Test Times by Post-ATPG Optimization of DFTMAX Ultra Patterns [More Info] Speaker: Richard Illman, Member of Technical Staff, Dialog Semiconductor | |
| 3:45 pm - 4:30 pm | Mission City 2 | Selective Ungroup Synthesis Approach in High Speed DSP Design [More Info] Speaker: Hailan Zhu, Principal Design Engineer, Broadcom | |
| 3:45 pm - 4:30 pm | Hall A3 | Shutdown with Agreements in a UVM Testbench [More Info] Speaker: Mark Glasser, Principal Verification Architect, NVIDIA | |
| 3:45 pm - 4:30 pm | Hall A2 | Using Formal Tools to Verify Datapath Designs During Various Phases of Processor Development [More Info] Speaker: Vigyan Singhal, Oski Technology | |
| 4:30 pm - 5:15 pm | Mission City 2 | Design for Reconfigurability [More Info] Speaker: Kalyana S Venkataraman, Hardware Design Engineer , Cavium | |
| 4:30 pm - 5:15 pm | Hall A2 | End-to-End Formal Verification Using VC Formal [More Info] Speaker: Nirabh Regmi, Microsoft | |
| 4:30 pm - 5:15 pm | Hall A3 | Simulation-Based Verification of Partial Reconfiguration in FPGAs [More Info] | |
| 4:30 pm - 5:15 pm | Ballroom H | Stuck at Pattern Generation Using Internal Clocking Procedure [More Info] Speaker: Ashok Mathur, Senior Member Technical Staff, AMD | |
| Verification Continuum III (FPGA & Prototyping) | |||
| March 22, 2017 | |||
| 11:00 am - 11:45 am | Room 209 | Widening the Scope and Adoption of FPGA-based Physical Prototyping at ARM [More Info] Speaker: Peter Fogl, Senior Engineer, ARM Ltd | |
| 11:45 am - 12:30 pm | Room 209 | Trapping the Hardest to Find Hardware Bugs in the Latest ARM Cores Using FPGA-based HAPS Debug Technologies [More Info] Speaker: Peter Gibbons, Senior FPGA Engineer, ARM Ltd. | |
| 2:00 pm - 2:45 pm | Room 209 | Achieving Optimized QoR with ProtoCompiler on Mixed HAPS-70 & HAPS-80 Systems [More Info] Speaker: Ramanan Sanjeevi Krishnan, NVIDIA Speaker: Sivarama Prasad Valluri, NVIDIA | |
| 2:45 pm - 3:30 pm | Room 209 | GPU Prototyping With HAPS [More Info] Speaker: Lance Tamura, Synopsys | |
| 3:45 pm - 4:30 pm | Room 209 | Effective Methodology for Latch-based Design – CPU Prototyping on HAPS Platform [More Info] | |
| Verification Continuum | |||
| March 22, 2017 | |||
| 11:00 am - 11:45 am | Hall A2 | Introduction to Reset Domain Crossings [More Info] Speaker: Sean O'Donohue, Synopsys | |
| 11:00 am - 11:45 am | Hall A3 | Performance for Productivity [More Info] Speaker: Sourabh Goyal, Prinicipal Verification Engineer, Xilinx | |
| 11:45 am - 12:30 pm | Hall A2 | Introduction to SpyGlass Lint Turbo for 3X Violation Reduction to Accelerate RTL Design Closure [More Info] Speaker: Aloke Das, Synopsys | |
| 11:45 am - 12:30 pm | Hall A3 | VCS Performance Innovations - Fine-Grained Parallelism and More! [More Info] Speaker: Kiran Maiya, Synopsys | |
| 12:30 pm - 2:00 pm | Hall A1 | Verification Lunch & Learn: SoC Leaders Verify with Synopsys [More Info] | |
| 2:00 pm - 3:30 pm | Hall A2 | Increase Your Verification Productivity with VC Formal [More Info] Speaker: Giovanni Auditore, Senior Technical Staff Member , STMicroelectronics Speaker: Anders Nordstrom, Synopsys | |
| 2:00 pm - 2:45 pm | Hall A3 | Reusable Compile Snapshot for Scaling Down Compilation Time Towards Modern SoC Verification [More Info] Speaker: Akshay Shukla, Sr. Engineer, eInfochips Inc | |
| 2:45 pm - 3:30 pm | Hall A3 | A Simple RTL IP Obfuscation Flow - Using Synopsys VCS, DC and Formality [More Info] Speaker: David Flynn, Fellow, ARM Ltd | |
| 3:45 pm - 4:30 pm | Hall A3 | Shutdown with Agreements in a UVM Testbench [More Info] Speaker: Mark Glasser, Principal Verification Architect, NVIDIA | |
| 3:45 pm - 4:30 pm | Hall A2 | Using Formal Tools to Verify Datapath Designs During Various Phases of Processor Development [More Info] Speaker: Vigyan Singhal, Oski Technology | |
| 4:30 pm - 5:15 pm | Hall A2 | End-to-End Formal Verification Using VC Formal [More Info] Speaker: Nirabh Regmi, Microsoft | |
| 4:30 pm - 5:15 pm | Hall A3 | Simulation-Based Verification of Partial Reconfiguration in FPGAs [More Info] | |
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