Thin Wafer Handling and Processing
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> Thin Wafer Handling and Processing


Tuesday, October 18, 2011, 8:00 AM PDT

Hosted by Yole Développement

Eric Mounier, MEMS Project Manager, Yole Développement


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Abstract and Speaker info below:

Consumer electronics are driving the need for smaller, higher performing, lower cost device configurations for use in applications such as memory or wireless devices. These new options, in turn, are pushing demand for a reduction in chip thickness from the traditional 500µ thickness to about 50 µm and even lower. Thin dies are driving the need for thin and even ultra-thin semiconductor wafers (below 50µm). Motivations for thin wafers are: reduced package size (e.g. for cell phones, the die thickness must be below 1.2 mm), better power dissipation, higher electrical performance and higher interconnect density.

For these reasons thin wafers will be used in more diverse applications such as MEMS, CMOS Image Sensors, 3D Packaging, Memories, RF Devices, Power Devices, LEDs … MEMS are always characterized by a wide range of process and technologies and these are certainly the applications where the widest range – nonstandard - of wafer thickness can be found.  In addition, to address the need for thinner sensors for cell phones applications, capping, sensitive elements and MEMS ASIC will get thinner over the next year, specifically inertial MEMS. For CMOS Image Sensors, BSI (Backside Illumination) now enables ~ 100% Fill-factor, opens the window area of CMOS sensor to higher Sensitivities or Higher Resolution. But we need to handle very thin layer for a BSI CIS, the active layer is < 10µ (4-6µ today, 2-3µ in the future). 3D stacking is definitively the next big thing for memory integration with wafers thickness as low as 25µ in 2016.

As wafer thickness is decreasing, ultra-thin wafers are less stable and more vulnerable to stresses, and dies can be prone to breaking and warping—not only during grinding but also at subsequent processing steps. To address these challenges new processes and – temporary - bonding technologies will be required for handling such fragile wafers, specifically to support the wafer during backgrinding and subsequent post-thinning processes. As tapes can no longer be used for ultra-thin wafers (main reasons are the non-uniformity of the tapes, the adhesion and the extreme flexibility), new wafer handling technologies have to be developed. We are at the very start of an impressive market growth for temporary bonding technology. Today, temporary bonding technologies are numerous with no clear winning scenario coming out today. We have identified at least 6 different technologies for wafer temporary bonding with carriers. Each one of these approach might have subtle different in terms of chemistry, carriers … Along with these approaches came also temporary bonding without carrier and reconstituted wafer for Fan Out WLP. So, the total number of approaches is more than 10 as per today. But this market is still in infancy and no clear temporary bonding technology is emerging. Many companies are competing to propose the best approach to achieve low cost, high temperature resistance, topography issues. As temporary bonding is a multi-disciplinary technology, it implies mastering know-how in process, chemistry and an understanding of the final application requirements. As a consequence, there are numerous collaborations running between tool makers, chemical players and substrates suppliers. Some companies are mastering both process and chemistry, but for others, partnerships are necessary.
The Webcast will highlight:

  • Motivations to go to thin, then ultra-thin wafers
  • Thin wafers applications
  • Thin wafers roadmap
  • Technical challenges associated to thin wafer manipulation
  • Overview for the different temporary bonding approaches
  • 2010-2016 market forecast for thin wafers and temporary bonding equipment
Dr. Eric Mounier has a PhD in microelectronics from the INPG in Grenoble. Since 1998 he is a cofounder of Yole Developpement, a market research company based in France. Dr. Eric Mounier is in charge of market analysis for MEMS, equipment and material. He is Chief Editor of Micronews and MEMS’Trends magazines (MEMS Technologies & Markets).


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