> Benefits and perspectives of Cu-pillar bumping
Wednesday, September 28, 2011, 8:00 AM PDT
Hosted by Yole Développement
Jean-Marc Yannou, Advanced Packaging, WLP & 3D System Integration Project Manager, Yole Développement
Abstract and Speaker info below:
Technology and market introduction to the new flip chip technology which helps high performance meet lower costs
Copper pillars were alternately introduced in volume production by a limited number of players for a limited number of applications: in 2003 in some WLCSP packages to enhance thermo-mechanical robustness, in 2006 in CPU flip chip packages to replace solder bumps with lead content, in 2006 as well in flip chip packages for RF power amplifiers, driven by their excellent electrical and thermal properties. But in 2010, copper pillar bumps made a new leap forward with their introduction in the application processors of smartphones.
Motivated by a combination of drivers Cu Pillars continue gaining traction across a wide range of applications. In fact Cu pillar flip chip is expected to continue to grow at a CAGR of 20% in terms of wafer counts in the coming 5 years. At this pace Cu pillar flip chip bumping is poised to become the interconnect of choice for advanced CMOS processes.
The arguments “for” are many:
- High electrical and thermal conductivity
- Better thermal cycling and electromigration reliability performance than solde
- Smaller pitches enable lower layer count laminates
- No UBM needed on Copper pads
- Higher z-height standoff allows for use of low-cost molded under fill (MUF)
- Gold wire bonding is becoming expensive due to the increase in the price of gold
- No major investment needed for wafer bumping
Driven by these advantages, the major OSATs are building capacity to produce more Cu pillar packages, which will provide access to Cu pillar flip chip technology to all companies involved in CPUs, GPUs and chipsets , to large FPGA and ASIC companies as well as to a growing number of IC types in mobile phones including power amplifiers, application processors and power management units.
There are still a number of package configurations and technology options to be chosen from to make a flip chip package with copper pillar (or column, as some call them) bumps, but this is already set to be a major trend in the semiconductor packaging industry, and one which will change it far beyond the traditional application areas of flip chip.
Jean-Marc Yannou joined Yole Developpement as technology and market expert in the fields of advanced packaging and Integrate Passive Devices. He has 15-years of experience in the semiconductor industry. He worked for Texas Instruments and Philips (then NXP semiconductor) where he served as Innovation Manager for System-in-Package technologies.