| Speakers: | Dr. Philippe Roussel, LED Senior Project Manager, Yole Développement |
| Raja M. Parvez, President, Chief Executive Officer and Director, Rubicon Technology |
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LEDs have already reached a sufficient price/performance level to enable massive adoption in LCD display applications. General lighting application will be the next and largest market for LED light sources. However, for most of the applications, LEDs are still too expensive. The industry consensus points toward the need for an additional 10x reduction in packaged LED cost of ownership expressed in $/lumen in order to compete broadly with incumbent technologies and enable massive adoption in most lighting application segments. To answer this demand, huge efforts have to be made all over the value chain, from the sapphire substrate to the final luminaire cost structure. Increasing the substrate diameter is one of these enabling technologies. 2009 saw the introduction of first industrial tools running 6” diameter for LED manufacture and this industry is now clearly moving toward larger substrate diameter. C-plan 3” and 4” already represent about 50% of the total surface shipped in 2011 and 6” is now reaching 5% of the production, thanks to companies such as LG, Samsung, Showa Denko, Osram or Lumileds who all moved to 6”.
This webcast will highlight:
- Main economics of the LED business and linked demand for sapphire substrates
- Including market metrics from 2009 to 2015 and in some cases to 2020
- Status and forecast of companies plan to move to 6” substrate
- Brief overview of tool makers and offer some perspective on competitive substrates such as SiC and Silicon
- Estimation of production cost of 6” sapphire using different growth methods (Kyro, CZ off-axis, CZ on-axis, EFG)
- Forecast and market metrics of the 6” sapphire wafer business to 2020
SPEAKERS:
Speaker:Jean-Marc Yannou, Advanced Packaging, WLP & 3D System Integration Project Manager, Yole Développement
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Technology and market introduction to the new flip chip technology which helps high performance meet lower costs
Copper pillars were alternately introduced in volume production by a limited number of players for a limited number of applications: in 2003 in some WLCSP packages to enhance thermo-mechanical robustness, in 2006 in CPU flip chip packages to replace solder bumps with lead content, in 2006 as well in flip chip packages for RF power amplifiers, driven by their excellent electrical and thermal properties. But in 2010, copper pillar bumps made a new leap forward with their introduction in the application processors of smartphones.
Motivated by a combination of drivers Cu Pillars continue gaining traction across a wide range of applications. In fact Cu pillar flip chip is expected to continue to grow at a CAGR of 20% in terms of wafer counts in the coming 5 years. At this pace Cu pillar flip chip bumping is poised to become the interconnect of choice for advanced CMOS processes.
The arguments “for” are many:
Performance
- High electrical and thermal conductivity
- Better thermal cycling and electromigration reliability performance than solder
Cost
- Smaller pitches enable lower layer count laminates
- No UBM needed on Copper pads
- Higher z-height standoff allows for use of low-cost molded under fill (MUF)
- Gold wire bonding is becoming expensive due to the increase in the price of gold
Legal
- Move to 100% lead-fre
Infrastructure
- No major investment needed for wafer bumping.
Driven by these advantages, the major OSATs are building capacity to produce more Cu pillar packages, which will provide access to Cu pillar flip chip technology to all companies involved in CPUs, GPUs and chipsets , to large FPGA and ASIC companies .as well as to a growing number of IC types in mobile phones including power amplifiers, application processors and power management units.
There are still a number of package configurations and technology options to be chosen from to make a flip chip package with copper pillar (or column, as some call them) bumps, but this is already set to be a major trend in the semiconductor packaging industry, and one which will change it far beyond the traditional application areas of flip chip.
SPEAKER:
Speaker: Eric Mounier, MEMS Project Manager, Yole Développement
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Consumer electronics are driving the need for smaller, higher performing, lower cost device configurations for use in applications such as memory or wireless devices. These new options, in turn, are pushing demand for a reduction in chip thickness from the traditional 500µ thickness to about 50 µm and even lower. Thin dies are driving the need for thin and even ultra-thin semiconductor wafers (below 50µm). Motivations for thin wafers are: reduced package size (e.g. for cell phones, the die thickness must be below 1.2 mm), better power dissipation, higher electrical performance and higher interconnect density.
For these reasons thin wafers will be used in more diverse applications such as MEMS, CMOS Image Sensors, 3D Packaging, Memories, RF Devices, Power Devices, LEDs … MEMS are always characterized by a wide range of process and technologies and these are certainly the applications where the widest range – nonstandard - of wafer thickness can be found. In addition, to address the need for thinner sensors for cell phones applications, capping, sensitive elements and MEMS ASIC will get thinner over the next year, specifically inertial MEMS. For CMOS Image Sensors, BSI (Backside Illumination) now enables ~ 100% Fill-factor, opens the window area of CMOS sensor to higher Sensitivities or Higher Resolution. But we need to handle very thin layer for a BSI CIS, the active layer is < 10µ (4-6µ today, 2-3µ in the future). 3D stacking is definitively the next big thing for memory integration with wafers thickness as low as 25µ in 2016.
As wafer thickness is decreasing, ultra-thin wafers are less stable and more vulnerable to stresses, and dies can be prone to breaking and warping—not only during grinding but also at subsequent processing steps. To address these challenges new processes and – temporary - bonding technologies will be required for handling such fragile wafers, specifically to support the wafer during backgrinding and subsequent post-thinning processes. As tapes can no longer be used for ultra-thin wafers (main reasons are the non-uniformity of the tapes, the adhesion and the extreme flexibility), new wafer handling technologies have to be developed. We are at the very start of an impressive market growth for temporary bonding technology. Today, temporary bonding technologies are numerous with no clear winning scenario coming out today. We have identified at least 6 different technologies for wafer temporary bonding with carriers. Each one of these approach might have subtle different in terms of chemistry, carriers … Along with these approaches came also temporary bonding without carrier and reconstituted wafer for Fan Out WLP. So, the total number of approaches is more than 10 as per today. But this market is still in infancy and no clear temporary bonding technology is emerging. Many companies are competing to propose the best approach to achieve low cost, high temperature resistance, topography issues. As temporary bonding is a multi-disciplinary technology, it implies mastering know-how in process, chemistry and an understanding of the final application requirements. As a consequence, there are numerous collaborations running between tool makers, chemical players and substrates suppliers. Some companies are mastering both process and chemistry, but for others, partnerships are necessary.
The Webcast will highlight:
- Motivations to go to thin, then ultra-thin wafers
- Thin wafers applications
- Thin wafers roadmap
- Technical challenges associated to thin wafer manipulation
- Overview for the different temporary bonding approaches
- 2010-2016 market forecast for thin wafers and temporary bonding equipment
SPEAKER:
Brice Le Gouic, Power Electronics Market & Technology Analyst, Yole Développement
Paul Kierstead, Director of Marketing, Cree Power Products
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Technical Trends :
We will review the PV Inverter as a system to analyze the technical trends and advancements in several key areas, micro-inverters and related compound semiconductor-based devices for conversion and the integration of some new functions. Functionalities tend to improve the global return on investment (ROI) of the PV plant, as well as efficiency and reliability or reducing cost:
- Anti-theft
- On-site aging effect measurement
- Voltage, current, temperature monitoring
- Protection, in case of maintenance
- Communication
At the plant level (PV inverter environment), architectures are slowly getting standardized, especially on the European market where feed-in tariffs (FIT), although less interesting, define a typical size of installation (3kW in France and Italy, about 5kW in Germany,…). Architecture of the industrial building-based PV plants are divided into two main “types”:
- Using up to 20kW inverters for installations up to 100kW
- Using large inverters for more than 100kW
The question remains as to the impact of these limiting architectures.
During this webcast we also hope to review some interesting trends in active power components used for PV inverters, as well as the implementation of new technologies such as Super Junction MOSFETs, SiC or GaN based devices. Finally we will also present initial results of our analysis on passive components, overviewing capacitors, resistors and others.
Market trends:
We will identify the market trends associated with some major market dynamics such as:
- Decrease of FITs in most attractive countries (Germany, France, Italy, Spain,…)
- Acceleration of signed contracts which has generated a shortage situation of largest PV inverter makers, like SMA, Kaco or Fronius.
- Big player response to shortages
- Delivery times
- Reinforcement of US players
- Entry of other players who used to be in train or UPS business
- Arrival of Asian players, each with a competitive advantage: cost (for Chinese players), efficiency and reliability (for Japanese players).
The Global PV market is still very attractive, even though more and more competitive. We will highlight these trends and provide some market forecasts while highlighting the geographic opportunities. How does the decreasing cost of the inverter affect the major players, does this provide opportunities for new players?
Last but not least, all the power optimization solutions are meeting issues to penetrate the market, for several reasons:
- Too expensive solutions
- Not very well defined position in the supply chain
- No clear advantages in dynamic conditions
However, those players are pushed by impressive investments and according the sales done by a majority, it is still hard to understand how their value is created and will be profitable, even if some of them seem to show good results.
Of course improving the efficiency of a PV plant is an added value, and now, the most challenging point will be to know their position in the supply chain: will they be a “unique type” of player, assuming that each of them claims a different technology and different advantages? Or will they be vertically integrated by the inverter makers?
SPEAKERS:
He was granted a Master of Science degree in semiconductor physics and microelectronics from the National Institute of Applied Sciences in Toulouse, France.
Paul Kierstead has been in the Semiconductor business since 1984. He has held engineering and marketing positions in the high speed interface and interconnect controller sectors and most recently has been dedicated to high efficiency power devices. He has lead effort in power market analysis, developed market and product strategies and has driven marketing business development efforts. Paul joined Cree SiC Power Products Group in 2008 as the Director of Marketing and Applications. In that role, Paul is responsible for Cree’s global SiC business development, applications support and new product strategy. Prior to joining Cree, Paul was employed by Fairchild and National Semiconductor. Paul is an avid golfer and enjoys boating with his family on the coast of his home state of Maine. Paul and his wife now reside in Morrisville, NC.
Dr. Peter L. Bocko, Chief Technology Officer , Corning Glass Technologies
Glass is a relatively new material to the semiconductor wafer-processing industry. Microfluidic chips and MEMS packaging have driven the initial demand for structured glass substrates re-using wafer-scale manufacturing techniques for etching cavities, channels and holes structures at the wafer-scale. Today, the demand for structured glass substrates is clearly surging, supported by the recent booming adoption of wafer-level-packaging techniques into new markets such as CMOS image sensors, camera module lenses, LED and semiconductor chip packaging applications.
The adoption of structured glass substrates is actually linked to the emergence of several unique wafer-processing platforms:
- Wafer Level Caps to protect sensor devices, create hermetic cavities at the wafer-scale
- Wafer Level Fluidic structures: to form channels, holes and functionalized surfaces to drive fluids at the chip level
- Wafer Level Optics to build lenses or spacer wafers for guiding, concentrating or diffracting light
- Glass support carriers for handling fragile /or very thin substrates during temporary-bonding & de-bonding operations
- Glass interposers substrates: the inner exceptional RF and electrical insulation properties of glass compared to plastic or silicon makes glass material today in a unique position to address the future challenges of lower cost, lower thickness, higher resolution IC packaging substrates
The goal of this editorial webcast will be to discover the following key features:
- Which applicationsare emerging for structured glass substrates today and tomorrow?
- What are the different types of glass (Borofloat, Alkaline, Glass-ceramics, etc…)? What are the advantages of glass substrates compared to ceramic, silicon or plastic alternatives?
- What are the different glass substrate processing techniques (sand blasting, etching, polishing, UV-embossing, laser heating, etc…) to structure and embed more functionality into glass substrates (such optical, fluidic, cavities, electrical via interconnects, etc…) ?
- Who are the key suppliers of blank and structured glass substrates? Which Glass foundries are able to structure glass substrates as a service today?
- Who are the key end-user companies driving the actual and future demand for structured glass substrates?
- How can glass substrates leverage an efficient infrastructure for large areas processing on Panel-size (possibly supported by the LCD industry)?
It’s exciting times at the moment for many glass suppliers and glass processors around the globe as this unique material is suddenly driving the attention of many different industries and for very different motivations. This informative editorial webcast will assess the status and perspectives of glass technology while presenting its unique properties leading its emergence into the traditionally “silicon-made” semiconductor wafer-processing worlds.
SPEAKER:
Bocko transferred to Product Development in 1988 to be technical leader for the LCD Project. He led the team that secured the qualification of non-polished code 7059 fusion glass in a first-generation customer process and later was project manager for the code 1737 composition development. In 1995, Bocko became worldwide manager of product engineering for Advanced Display Products directing technology activities for the commercialization of a range of new products including codes 1737, 1737G and polysilicon substrates. He led the collaborative design process with customers and Corning R&D that culminated in the delivery of the EAGLE2000® glass family. Bocko returned to Science & Technology in 1998 as business technology director for Advanced Display Products delivering substrate technologies for three generations of customer AMLCD manufacturing and the emerging LCD-TV application. In January 2004, he was appointed to the position of division vice president and director, Commercial Technology, and in May 2006, named division vice president, Display Futures, and then chief technology officer, East Asia in September 2007.
Bocko was appointed to his current position of chief technology officer, Corning Glass Technologies in October 2010.
Bocko received a bachelor’s degree in chemistry from the State University College at Oswego and master’s and doctorate degrees in physical chemistry from Cornell University. In 2009, Peter received a Special Recognition Award from the Society for Information Display (SID) recognizing his central role in delivering innovative, high-performance glass substrates for the display industry. He holds ten US patents.
Speaker: Milan Rosina, Photovoltaic Technologies Market & Technology Analyst, Yole Développement
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Although cumulative High Concentration Photovoltaics (HCPV) installed capacity represents only about 30 MW (less than 1% of the total PV market), it is currently at an inflection point to be deployed in utility-scale applications in some sunny locations and could surpass 1GW of yearly installed capacity in 2018. HCPV system technology providers like Amonix, Soitec/Concentrix and SolFocus have recently developed significant installation project pipelines. Such a growing market reveals the strong attention of numerous industrial players mainly coming from LED and microelectronic industry that see in HCPV the opportunity to use their expertise in III-V semiconductor technology to diversify their business. However, the HCPV technology is in general still struggling with low bankability and low interest of utility companies mainly due to short system field performance track records and the high cost of installed system. Beside of going to mass production of HCPV systems, a substantial system cost reduction could be enabled for instance by using of larger (6-inch) substrates for solar cell growth, by increasing the cell efficiency over 40% using new cell material, structures or deposition techniques, by increasing the light concentration ratio, by improving the module design, etc. Therefore, there is still a lot of room for companies coming with novel approaches. Much effort has to be made in all technological segments to develop more efficient, more reliable and durable HCPV systems for a competitive price and to provide independent data about their field performance at different locations.
This webcast will highlight:
- Advantages and drawbacks of different solar technologies for electricity production.
- Main market technology drivers and market barriers for the HCPV development.
- Levelized Cost of Electricity for HCPV and main factors for its reduction.
- Overview of all elements of the HCPV value chain (wafer, epiwafer, cell, optics, module receiver, tracker,…), their requirements and technological challenges.
- Brief overview of technology suppliers for each element of an HCPV system.
- Forecast and market metrics of the HCPV business until 2018.
SPEAKER:
Speaker: Alexandre Avron, Power Electronics & Compound Semiconductors Market & Technology Analyst, Yole Développement
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Energy conversion is under the spotlight and the technology inside is moving faster than ever:
SiC was the 1st innovative material, outperforming Silicon in all domains when used in power switches, but it has taken more than 10 years for the first switches to be released. Most of the big manufacturers are involved in SiC development (Infineon, ST Microelectronics, Rohm…) and their unique strategies can be the game changer. For example, Fairchild gave up all developments 3 years ago, and then this year to prepare a comeback in the SiC business purchased TranSiC.
In addition another material challenger is now present, GaN, widely used in LED’s, has emerged in power electronics applications. It has its pros and cons but it is very attractive for many applications (MV power supplies, EV/HEV). Several start-ups are developing solutions (EPC, Transphorm, Powdec) as well as bigger players like International Rectifier.
On the other side, Silicon is still here. Improvements are made on MOSFETs and IGBTs at a competitive cost. Super Junction structure is eating market shares with CoolMOS® or MDmesh® products and four players revealed their portfolio in the last 18 months (Fuji electric, Alpha&Omega Semiconductor, Vishay and Renesas).
This complicated landscape brings lots of questions:
- Where are these technologies positioned?
- Which applications could they target? Which will they penetrate in the future?
- How are they positioned one versus the other?
- What are manufacturers’ strategies and roadmaps?
- What will be the impact in system design, BoM and manufacturing?
In this webcast we will provide key facts, assumptions and market metrics and forecasts to answer these questions.. Obviously the supply chain is critical to the entire market review, while the system manufacturers will want to understand the impact of these new devices , and in turn the device and equipment manufacturer will want to understand their options to provide the right solutions, at the right time.
SPEAKER:
